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STA Based IP Block Timing Extraction

Add comment January 31st, 2015

[January 2015] PicoCraft delivered STA services to Timing Capture parameters necessary for IP Block Timing Extractions in system level. IP Blocks were  in 16nm and 20nm technologies.

16nm IP Block Implementation

Add comment July 1st, 2014

[July 2014] PicoCraft completed Physical Design and Timing Verification for 16 nm IP Blocks in DSP application.

20nm IP Block Signoff

Add comment December 30th, 2013

[December 2013] PicoCraft delivered timing signoff for 20 nm communication IP block designs.

Full Chip Synthesis Consulting Service

Add comment April 30th, 2013

[April 2013] PicoCraft completed design service of Full chip and block logic and DFT Synthesis for communication chip designs.

IP Timing Characterization Flow

Add comment May 30th, 2012

[May 2012] PicoCraft  developed and delivered STA based full timing characterization flow for processor IP block to support proprietary application system.

Full Chip SoC Timing Signoff Flow

Add comment September 30th, 2011

[September 2011] PicoCraft delivered an automated full chip SoC Timing Signoff Flow supporting multiple IPs with separate Library implementations. Flow was developed in Goldtime STA tool.

28nm IP Block Implementation

Add comment December 30th, 2010

[December 2010] PicoCraft delivered Timing Sign-off and Multi-Scenario ECO flow for 28nm IP designs.  Established a consistent Timing Closure methodology for all IP blocks.

FrontEnd Chip Implementation

Add comment July 30th, 2010

[July 2010] PicoCraft delivered Front-end Synthesis flow, DFT Implementation and STA signoff flow for 45nm communication chip designs.

45nm Timing Constraints and Signoff

Add comment August 30th, 2009

[August 2009] PicoCraft completed Timing Constraints and STA Signoff for 45nm SOC in consumer product design.

Timing Bring-up and CDC Analysis

Add comment January 31st, 2009

[January 2009] PicoCraft provided Timing bring-up and automation support for 65nm and 45nm SOC product bring-up. PicoCraft provided the Clock Domain Crossing (CDC) analysis of large scale SOC design.

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